1. Field of the Invention
The invention relates to an image pickup device having a solid-state image pickup device and, more particularly, to a method of reducing noises contained in an image signal which is outputted from an image pickup device.
2. Description of the Related Art
According to a CCD (Charge Coupled Device) image pickup device among solid-state image pickup devices, although sensitivity is high and an amount of white blemish is small, the white blemish upon photographing of the high sensitivity is large. According to the CCD image pickup device, when a high-luminance object such as a spotlight or the like is photographed, excess charges leak and flow into a vertical transfer path from a photodiode of a pixel which has photographed the spotlight, an image signal which is proportional to illuminance of the spotlight is multiplexed to all pixels in the same vertical direction as that of the pixel which has photographed the high-luminance object, and a white vertical line called a vertical smear occurs. If an accumulating surface is provided outside of an image pickup surface of the CCD image pickup device and a vertical transfer speed is raised, the vertical smear decreases. However, if the accumulating surface is provided, an area of the CCD image pickup device is increased and its costs rise. If the vertical transfer speed is raised, electric power consumption is also increased and the white blemish increases. Further, it is necessary to deeply form the photodiode in order to raise near-infrared sensitivity of the CCD image pickup device, so that the white blemish increases.
Hitherto, in order to reduce an influence of the white blemish of an optical black pixel portion, vertical pixel signals of outputs of 12 lines of a optical black pixel (Vertical-Optical Black; hereinbelow, abbreviated to “V-OB”) portion of the CCD image pickup device are averaged and stored as a signal of one line, and the stored signal is subtracted from output signals of effective pixel portions of the solid-state image pickup device (refer to JP-A-7-067038).
Owing to an increase in integration degree of a digital signal processor, such a process for storing the output signals of a plurality of lines and arithmetically operating them can be easily realized not only in a memory integrated DSP for use of a video image but also in a reasonable general-purpose FPGA (Field Programmable Gate Array).
Further, an FEP (Front End Processor) having therein a CDS (Correlated Double Sampling) for removing noises from a signal outputted from the CCD, a dark current correction, an AGC (Automatic Gain Control), and an ADC (Analog Digital Converter) for converting the signal into a digital video signal Vi has been spread. Although a gradation of the ADC of the FEP has conventionally been equal to 10 bits, a gradation of 12 bits or 14 bits is generally used and a processor having a gradation of 16 bits has also been realized as a product. The FEP in which the gradation of the ADC is set to 22 bits and the AGC is arranged after the ADC has also been realized as a product.
Moreover, according to an Electron Multiplying—CCD (hereinbelow, abbreviated to “EM-CCD”), since the sensitivity can be raised by combining the EM-CCD with an electron cooling unit, quasi-motion image monitoring without an illumination for photographing at night using visible light and near-infrared rays can be performed.